DZD450型真空包裝機設計含8張CAD圖

DZD450型真空包裝機設計含8張CAD圖,dzd450,真空,裝機,設計,cad 任務書 XX 學院 XXXX專業(yè) 論文題目 DZD450型真空包裝機設計 學生姓名 XX 學 號 XX 起訖日期 20XX.2.20-2012.6.8 指導教師姓名（簽名） 指導教師職稱 XX 指導教師工作單位 XXXXXXXXXXXX 院（系）領導簽名 下發(fā)任務書日期 ： 20XX年2月 20日 題 目 DZD450型真空包裝機設計 論文時間 20XX年2月20日至 20XX年6月1日 課題的主要內(nèi)容及要求(含技術要求、圖表要求等) 根據(jù)以下參數(shù) 1. 熱封條數(shù)：兩條 2. 真空室絕對壓強：≤ 1.332KPa 3. 最大封口有效尺寸(長×寬) mm：450×10 4. 加熱溫度調節(jié)范圍（℃） ：90～240 5. 加熱為時間調節(jié)范圍(S) :1～10 6. 包裝能力（次/小時）：180～250 7. 電源（三相四線制）：380V/50Hz 8. 額定功率（KW）:1.3 9. 控制特征：人工上袋自動控制 設計一種真空包裝機，完成總裝圖及零件。編寫設計說明書；完成專業(yè)外文資料翻譯1份。 課題的實施的方法、步驟及工作量要求 設計方法：學生在指導教師的指導下，利用所學的課程并自學有關知識，掌握機械設計的特點、方法，借助《機械設計手冊》等技術資料，完成本機設計。 設計步驟：調研收集設計資料——根據(jù)所給定的參數(shù)制定總體設計方案——完成總裝圖及部裝圖——完成零件圖——編寫設計說明書。 工作量要求：設計圖紙工作量合計3張零號圖紙（A0-2,A1-0,A2-1,A3-1,A4-13）；畢業(yè)設計說明書不少于8000漢字；外文資料原文(與課題相關的1萬印刷符號左右)，外文資料翻譯譯文（約3000漢字）。 指定參考文獻 [1]屈能勝.我國食品包裝機械發(fā)展綜述[M].輕工機械,2005.02 [2]金國斌.現(xiàn)在包裝技術[M].上海：上海大學出版社,20001.4 [3]錢俊，余洗，劉冬林.特種包裝技術[M].北京：化學工業(yè)出版社。2003.11 [4]徐灝等.機械設計手冊[M].北京:機械工業(yè)出版社，1991 [5]文耀平.真空包裝機加熱封口變壓器設計計算方法[J].設計探討，1994 [6]王朝文.電熱電器的設計制造與使用維修[J]，北京：機械工業(yè)出版社，1987 [7]習培松.張道林，四連桿真空包裝機幾何參數(shù)的計算[J].農(nóng)機與食品機械，1998 [8]王萍.真空包裝機氣路系統(tǒng)設計原理[J].包裝與食品機械，1998 [9]甘永利.幾何公差與檢測[M].上海：上海工業(yè)出版社，2004 [10]成大先.機械設計手冊（第七卷）[M].北京:化學工業(yè)出版社,2002 [11]濮良貴,紀名剛主編.機械設計（第七版）[M].北京：高等教育出版社,2001 畢業(yè)設計(論文)進度計劃(以周為單位) 第 1 周（2012年 2月20日----2012年 2 月 26 日）： 下達設計任務書，明確任務，熟悉課題，收集資料，上交外文翻譯、參考文獻和開題報告。 第2周——第8周（2012年 2 月 27 日----2012年4 月 15 日）： 制定總體方案，繪制總裝圖草圖。 第 9 周——第14周（2012年4月16 日----2012年 5月 27日）： 修改并完成總裝圖及部裝圖，完成有關零件圖的設計。 第15 周——第 16 周（2012年 5 月28日----2012年 6 月5 日）： 編寫設計說明書 第 16 周（2012年 6月 6日----2012年6 月 8 日）： 準備答辯 備注 開題報告 題　　目 DZD450型真空包裝機設計 學生姓名、學號 沈揚 B08152067 專業(yè) 機械設計制造及其自動化（數(shù)控技術） 指導教師姓名 龐偉 職稱 副教授 一．課題背景和意義 包裝為在流通過程中保護產(chǎn)品，方便儲運，促進銷售，按一定的技術方法所用的容器、材料和輔助物等的總體名稱;也指為達到_卜述目的在采用容器，材料一和輔助物的過程中施加一定技術方法等的操作活功。一件產(chǎn)品一般要以商品的形式經(jīng)過流通后完好無損且保質保量地到達顧客手中，才能體現(xiàn)共功能價值和經(jīng)濟價值。沒有包裝的產(chǎn)品難以儲存，運輸和銷售。包裝是隨著人類經(jīng)濟活功的發(fā)展而發(fā)展的。在當前社會，需要包裝的物品種類己經(jīng)越來越多，同時對包裝機械的要求也越來越高。高精度，高質量，高效率的包裝機往往能大幅度地增加一個企業(yè)的市場競爭力。包裝機的引入甚至可以改變一個行業(yè)的生存面貌。中國白改革開放以來，包裝機械行業(yè)得到了允分的發(fā)展，取得的成就也很人，然而因為起步晚，對比國外先進包裝機械仍有小小差距，所以在技術領域仍然有廣闊的提升空間二這就需要我們對包裝機械行業(yè)給一子足夠的重視和支持?；诖耍覀兺ㄟ^劉一本課題的不斷深入研究，能夠在鞏固和鍛煉自身專業(yè)技能，熟練運用所學知識完成課題的同時，也要對包裝機械行業(yè)從分類與結構組成到它未來的發(fā)展趨勢有一個全局的了解。 當世界各國都規(guī)定肉制品不能使用硝酸鹽和亞硝酸鹽作為防腐劑后，真空包裝得到迅速的推廣應用。使用產(chǎn)品范圍很廣，如火腿、香腸、魚糕、咸菜、調味魚塊、鮮肉、冷凍牛排、可蒸煮袋熟肉制品、烘烤食品、果品、土特產(chǎn)品、藥材等;后來推廣到醫(yī)療器械、藥品的無菌包裝、化學品、精密儀器、服裝、五金產(chǎn)品、電子元件、軍工產(chǎn)品等各種固體、粉末裝物體、液體、固液混合體包裝。 隨著我國經(jīng)濟的日益發(fā)展壯大，包裝工業(yè)也以年均18%的速度快速發(fā)展，但與發(fā)達國家相比，無論在產(chǎn)品品種、技術水平和產(chǎn)品質量方面都有很大差距。在我國包裝工業(yè)快速發(fā)展的進程中，大量技術含量高的成套設備仍依靠進日。我國包裝機械對國外高端技術的過度依賴，己成為嚴重制約我國包裝工業(yè)持續(xù)、穩(wěn)定發(fā)展的隱憂。鑒于以上原因，且包裝行業(yè)又屬于配套行業(yè)，涉及國民經(jīng)濟的許多領域，特別是食品行業(yè)與飲料行業(yè)，更是有賴于包裝行業(yè)的技術進步、配套服務，因此，我們不能再忽視包裝機械落后狀況對我國包裝行業(yè)整體發(fā)展的負面影響。 真空包裝機是將包裝袋內(nèi)抽成低真空后，當即自動封口。由于袋內(nèi)的真空度高，殘留的空氣少，可抑制細菌等微生物的繁殖，能夠延長儲存期，防止食品腐敗。對某些松軟的食物，經(jīng)過真空包裝后可縮小體積。從而可使包裝物品達到“四防、兩省、一保質”的特點:即防潮、防霉、防污染、防氧化、省容積、省運費、延長儲存期。食品包裝中肉類是最適合真空包裝的。采用高度防透氧的薄膜—聚偏乙烯、聚酞胺、聚醋、涂以丙烯晴作為真空包裝材料，可使鮮肉在包裝內(nèi)處于無菌狀態(tài)，使其貨架壽命延長1倍。各種塑料復合薄膜袋或鋁箔復合薄膜袋等復合材料也適用于真空包裝。 真空包裝機是用于包裝產(chǎn)品，使產(chǎn)品增長其保質期，增加產(chǎn)品美觀度的一種機械。真空包裝技術可以提高商品的使用價值，防腐、防潮、防銹蝕，減少損耗，節(jié)約貯運費用，有利于健康。真空包裝技術廣泛用于食品、藥品、電子儀器、精密儀表、化工產(chǎn)品等行業(yè)。人們膳食結構的調整和飲食習慣的改變，我國經(jīng)濟持續(xù)發(fā)展，促使了食品加工的快速發(fā)展，增加了高品質的包裝機械和食品加工機械的需求。真空包裝己經(jīng)廣泛的推廣使用。低成本、智能化、高品質是食品包裝機械的發(fā)展趨勢。 一臺雙室機可相當于兩臺單室機，但較兩臺單室機小，重量輕，可輪番作業(yè)，使準備工作與包裝時間重合，因此較單室的工作效率較高，雖工作周期不變，但是排放包裝件的時間與自動循環(huán)時間重合，效率可提高，成為真空包裝機的又一主導產(chǎn)品。目前國內(nèi)現(xiàn)有的設備存在嚴重的缺陷，例如:封口性能不好、真空室密封不好、包裝袋的真空度不高、四連桿帶動上箱室的運動不平穩(wěn)、部件間連接不好、機構不可靠等缺陷，達不到理想的生產(chǎn)狀態(tài)。鑒于這種情況，參考了一些相關的科技資料，在現(xiàn)有的設備的基礎上，本次畢業(yè)設計對一種現(xiàn)有單蓋雙工位真空包裝機進行了改進設計。單蓋雙工位真空包裝機的關鍵設備是熱合部件和四連桿機構，它們決定了包裝袋的封口性能。因此這里所作的改進也是主要針對這兩部分進行的。 本課題將根據(jù)包裝機的功能要求和工藝分析，參考相關的資料，分析目前真空包裝設備的不足，對現(xiàn)有的單蓋雙工位真空包裝機進行了改進設計。主要的改進如下:重新選用了熱封變壓器，提高了封口質量;對上工作室的密封槽、密封條進行了重新設計，改善了真空室的密封性;對四連桿機構進行重新設計，改善了上真空室運動的平穩(wěn)性和靈活性。確定運動原理圖，機械系統(tǒng)示意圖，初定真空包裝機的結構形式。重點包括真空包裝機包裝帶供送機構設計，部件結構合理性分析和設計計算。主要零件的結構分析、材料選擇、公差配合選擇及技術要求說明。 由于實踐經(jīng)驗的欠缺和知識的局限性，該設備的實際工作情況及可用性還有待于實踐的檢驗 二．文獻綜述 課題依據(jù) 1、 熱封條數(shù)：兩條 2、 真空室絕對壓強：<1.332Kpa 3、 最大封口有效尺寸（長*寬）mm：450*10 4、 最大封口有效范圍（℃）：90~240 5、 加熱時間調節(jié)范圍（S）：1~10 6、 包裝能力（次/小時）：180~250 7、 電源（三相四線制）：380V/50Hz 8、 額定功率（KW）：1.3 9、 控制特征：人工上袋自動控制 設計方法： 學生在指導教師的指導下，利用所學的課程并自學有關知識，掌握機械設計的特點、方法，借助《機械設計手冊》等技術資料，完成本機設計。 設計步驟： 調研收集設計資料——根據(jù)所給定的參數(shù)制定總體設計方案——完成總裝圖及部裝圖——完成零件圖——編寫設計說明書。 工作量要求： 設計圖紙工作量合計3張零號圖紙（A0-2張，A1-2張，A2-0張，A3-0張，A4-0張，電子手繪-若干）；畢業(yè)設計說明書不少于8000漢字；外文資料原文(與課題相關的1萬印刷符號左右)，外文資料翻譯譯文（約3000漢字）。 三．參考文獻 [1]屈能勝.我國食品包裝機械發(fā)展綜述[M].輕工機械,2005.02 [2]金國斌.現(xiàn)在包裝技術[M].上海：上海大學出版社,20001.4 [3]錢俊，余洗，劉冬林.特種包裝技術[M].北京：化學工業(yè)出版社.2003.11 [4]徐灝等.機械設計手冊[M].北京:機械工業(yè)出版社，1991 [5]文耀平.真空包裝機加熱封口變壓器設計計算方法[J].設計探討，1994 [6]王朝文.電熱電器的設計制造與使用維修[J]，北京：機械工業(yè)出版社，1987 [7]習培松.張道林，四連桿真空包裝機幾何參數(shù)的計算[J].農(nóng)機與食品機械，1998 [8]王萍.真空包裝機氣路系統(tǒng)設計原理[J].包裝與食品機械，1998 [9]甘永利.幾何公差與檢測[M].上海：上海工業(yè)出版社，2004 [10]成大先.機械設計手冊（第七卷）[M].北京:化學工業(yè)出版社,2002. [11]濮良貴,紀名剛主編.機械設計（第七版）[M].北京：高等教育出版社,2001. 學生簽名： 年 月 日 指導教師批閱意見 （指導教師應對課題研究的思路、方法、對策、措施和預期成效等做出評價，并提出具體的改進意見） 指導教師簽名： 年 月 日 注：理工類學生偏重于對課題相關知識的理解和實施方案的框架結構，文管類學生偏重于對文獻資料的理解與綜述。表格欄高不夠可自行增加。 4 Stresa, Italy, 25-27 April 2007 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS Nicolas Abelé1,3, Daniel Grogg1, Cyrille Hibert2, Fabrice Casset4, Pascal Ancey3, Adrian M. Ionescu1 1LEG, Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 2CMI (EPFL), 3ST Microelectronics, France, 4CEA-LETI MINATEC, France ABSTRACT A new Room Temperature (RT) 0-level vacuum package is demonstrated in this work, using amorphous silicon (aSi) as sacrificial layer and SiO2 as structural layer. The process is compatible with most of MEMS resonators and Resonant Suspended-Gate MOSFET [1] fabrication processes. This paper presents a study on the influence of releasing hole dimensions on the releasing time and hole clogging. It discusses mass production compatibility in terms of packaging stress during back-end plastic injection process. The packaging is done at room temperature making it fully compatible with IC-processed wafers and avoiding any subsequent degradation of the active devices. 1. INTRODUCTION MEMS resonators performances have been demonstrated to satisfy requirements for CMOS co-integrated reference oscillator applications [2-3]. Different packaging possibilities were proposed in previous years using either a 0-level approaches [4, 5] or wafer bonding approaches [6]. According to industry requirements, 0-level thin film packaging using standard front-end manufacturing processes is however likely to be the most cost-efficient technique to achieve vacuum encapsulation of MEMS components for volume production. 2. DEVICE DESCRIPTION AND PACKAGING DESIGN The packaging process has been done on a MEMS resonator having MOSFET detection [1]. The device is based on a suspended-gate resonating over a MOSFET channel which modulates the drain current. The advantage of this technique is the much larger the output detection current than for the usual capacitive detection type, due to the intrinsic gain of the transistor. The RSG-MOSFET device fabrication process and performances were previously described in [7]. The process steps are presented in Fig. 1, where a 5μm thick amorphous silicon (aSi) layer is sputtered on the already released MEMS resonator followed by a 2μm RF sputtered SiO2 film deposition. A quasi-zero stress aSi film deposition process has been developed; the quasi- vertical deposition avoids depositing material under the beam lowering the releasing time. Releasing holes of 1.5μm were etched through the SiO2 layer and the releasing step is done by dry SF6 plasma. Due to pure chemical etching, high selectivity of less than 1nm/min on SiO2 was obtained. The holes were clogged by a non- conformal sputters SiO2 deposition at room temperature. Fig. 1 Schematic of the 0-level vacuum package fabrication process of a RSG-MOSFET Packaging process has been performed on the metal-gate SG-MOSFET and Fig. 2a shows an SEM picture of a released AlSi-based RSG-MOSFET with a 500nm air- gap, a beam length and width of respectively 12.5μm and 6μm with a 40nm gate oxide. A vacuum packaged RSG- MOSFET is shown in Fig. 2b highlighting the strong bonds of the re-filled releasing hole after clogging. Cross section of a releasing hole in Fig. 2c shows more than 1μm bonding surface to ensure cavity sealing. A FIB cross section in Fig. 2d shows the suspended SiO2 ?EDA Publishing/DTIP 2007 ISBN: 978-2-35500-000-3 Nicolas Abelé, Daniel Grogg, Cyrille Hibert, Fabrice Casset, Pascal Ancey, Adrian M. Ionescu 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS membrane above the suspended-gate. The vacuum atmosphere inside the cavity is obtained by depositing the top SiO2 layer under 5x10-7mBar given by the equipment. Suspended- Gate Drain Source Bulk contact a) 10 μm Drain Source Suspended- Gate 6μm 1μm b) SiO2 c) 1μm Hole diameter 1.5μm Vacuumed cavity 1um SiO2 d) Drain Suspended- Gate 50μm Fig. 2 SEM pictures of a) AlSi-based RSG-MOSFET, b) Top view of a SiO2 cap covering the RSG-MOSFET, c) Cross section of releasing holes filled with sputtered SiO2, d) FIB cross section of the packaged RSG- MOSFET, material re-deposited during the FIB cut is surrounding the suspended-gate and the SiO2 membrane. The slightly compressive SiO2 membranes show very good behavior for the thin film packaging, as seen in Fig.3 where cavities were formed on large opening size. During the clogging process, due to the highly non- conformal deposition, the amount of material entering in the cavity has been measured to be only 80nm compared to the 2.5μm oxide deposited. Residues inside the cavity are confined in an 8-to-10μm diameter circle, but strongly depend on the topology inside the cavity. The oxide thickness needed to clog the holes strongly depends on the hole width-over-height ratio, which therefore determines the amount of residues in the cavity. 40μm SuspendedSiO2 membranes a) 2μm 1.1μm aSi0.5μm wet oxide 4.5μm sputtered SiO2 b) Fig. 3 a-b)Cross section of a 2um SiO2 suspended membrane having a releasing hole clogged by a 2.5μm SiO2 sputtering deposition 3. EFFECT OF OPENING SIZE ON RELEASING RATE AND CLOGGING EFFECT Etching rate variation on aSi related to the hole opening size and the aSi thickness is shown in Fig. 4. Small holes openings decrease the etching rate. A dual underetching behavior due to aSi thickness variation and holes diameters is observed after a 2 min. release step: for a small hole aperture (2μm diameter), exposed surface factor is dominant and etching rate is 3 times greater for the thin aSi. However for large openings (9μm diameter) for which underetch distance is more important, path factor representing the lateral opening height for species ?EDA Publishing/DTIP 2007 ISBN: 978-2-35500-000-3 Nicolas Abelé, Daniel Grogg, Cyrille Hibert, Fabrice Casset, Pascal Ancey, Adrian M. Ionescu 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS to reach aSi becomes important and then etching ratio decreases to 1.3. 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 Hole diameter (um) Un de re tc h r at e ( um /m in) 1.1um aSi 3.3 um aSi Fig. 4 Underetch rate for various releasing holes diameters with amorphous silicon sacrificial layers of 1.1μm and 3.3μm, after 2min. releasing. After release, encapsulation is performed by sputtered deposition of SiO2 under high vacuum of 5x10-7mbar using the intrinsic, non-conformal deposition to clog holes, as shown in Fig. 5. Clogging effect is strongly material dependent and is related to the sticking coefficient that defines probability for a molecule to stick to the surface. The coefficient is below 0.01 for LPCVD Poly-Si but 0.26 for SiO2, therefore being more suitable for clogging purpose. SiO2membrane 2μm Clogging Holeaperture SiO2redeposition Remaining aperture Fig. 5 Schematic of a cross section of the SiO2 membrane clogged by SiO2 sputtering deposition Hole clogging has a strong dependence on the opening aspect ratio as presented in Fig. 6. Holes with diameter- over-height aspect ratio below 1 are clogged for SiO2 thickness of 2μm. Hole with opening ratio of 1.5 could only be clogged for a 3μm thick SiO2 deposition. The hole clogging rate is measured to be 330nm per deposited micron of SiO2. 0 1000 2000 3000 4000 0 1 2 3 Opening aspect ratio Re m ain in g ap er tu re (n m ) 2μm SiO2 Initial SiO2 membrane thickness = 2μm 3μm SiO2 Re ma ini ng ap er tu re (n m) Fig. 6 hole clogging effect depending on the diameter- over-height ratio in the 2μm SiO2 membrane (Right). Remaining aperture diameter (in nm) for 2μm and 3μm SiO2 deposition for hole clogging. The effect of hole geometry on underetch rate and clogging has been studied on square and rectangular holes in Fig.7. Rectangular opening has a quasi identical underetching than square shape of the same opening area, while clogging is 10 times more important. 0 5 10 15 20 25 30 35 0 5 10 15 20 Relasing time (min) Un de re tc h ( um ) 2um 2um x etching direction y etching direction x y x x Fig. 7 Underetch length after 16min release for 29.1μm2 square and rectangle release holes (red dotted rectangles). The initial SiO2 thickness is a 2μm and the thickness of aSi is 1.1μm. Remaining hole size after 2.5μm SiO2 deposition is 1.4μm for the square and 140nm for the rectangle. 4. PACKAGING ISSUES FOR PRODUCTION ENVIRONMENT For industrial production of integrated MEMS, 0-level package has to sustain plastic molding, which corresponds to an isostatic pressure of around 100Bar. Encapsulation film thickness has been designed to lower the impact of the pressure during molding. FEM simulations done with Coventor? in Fig. 8 show that the ?EDA Publishing/DTIP 2007 ISBN: 978-2-35500-000-3 Nicolas Abelé, Daniel Grogg, Cyrille Hibert, Fabrice Casset, Pascal Ancey, Adrian M. Ionescu 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS molding-induced package deflection is reduced to 25nm, having a 4.5μm thick SiO2 film, which makes it compatible with standard industrial back-end processes. 0 1.5 13 19 25 nm Displacement: a) Coventor? 0 0.4 0.8 1.2 1.6 MPa Stress: b) Coventor? Fig. 8 FEM modelling of the packaged resonator under applied isostatic pressure mimicking plastic injection process step. Effect of LTO and PECVD nitride materials on capping deflection under molding stress are presented in Table I. Membrane thickness can then be optimized to lower the molding-induced deflection by considering Young’s modulus and maximum stress before failure of the two materials. Structural layer material LTO Nitride PECVD Film thickness 4.5μm 2.5μm Max. stress before failure 2GPa 9GPa Stress due to molding 1.6MPa 4MPa Molding-induced deflection 25nm 36nm Table I. FEM simulations of the structural layer thickness needed to sustain plastic molding over 0-level packaging composed of a 30μmx30μm membrane. Comparison with PECVD nitride thickness needed to induce the same deflection. On the developed process flow, further investigations on vacuum level and long term stability still to be studied in order to fully characterize the packaging. This characterization can either be done directly by using helium leakage test [9], or indirectly by actuating the packaged resonator for which quality factor is directly related to the vacuum level. 5. CONCLUSION A novel 0-level packaging process was presented using aSi as sacrificial layer and SiO2 as encapsulating layer. RSG-MOSFET resonators have been successfully encapsulated under high vacuum. Impact of back-end-of- line industrial process over the encapsulation has been investigated, resulting in optimal cover thickness needed to sustain plastic molding. Influence of hole dimensions on releasing time and clogging effect for encapsulation were investigated, and optimized packaging parameters are identified for this process. . 11. REFERENCES [1] N. Abelé et al., "Ultra-low voltage MEMS resonator based on RSG-MOSFET ", MEMS ’06, pp. 882-885, 2006 [2] V. Kaajakari et al., "Low noise silicon micromechanical bulk acoustic wave oscillator", IEEE International Ultrasonics Symposium, pp. 1299- 1302, 2005 [3] Y.-W. Lin et al., “Low phase noise array-composite micromechanical wine-glass disk oscillator,” IEDM ’05, pp. 287-290, 2005 [4] N. Sillon et al., Wafer Level Hermetic Packaging for Above-IC RF MEMS: Process and Characterization, IMAPS 2004 [5] B. Kim et al.,, "Frequency Stability of Wafer-Scale Encapsulated MEMS Resonators," Transducers '05, vol. 2, pp. 1965-1968, 2005 [6] V. Kaajakari et al., "Stability of wafer level vacuum encapsulated single-crystal silicon resonators", Sensors and Actuators A: Physical, Vol. 130-131, pp. 42-47, 2006 [7] N. Abelé et al., "Suspended-Gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor ", IEDM ’05, LATE NEWS, pp. 479-481, 2005 [8] S. Frédérico et al.,”Silicon sacrificial layer dry etching (SSLDE) for free-standing RF MEMS architectures”, MEMS ’03, pp. 570- 573, 2003 [9] I. D. Wolf at al., "The Influence of the Package Environment on the Functioning and Reliability of Capacitive RF-MEMS Switches," Microwave Journal, vol. 48, pp. 102-116, 2005. ?EDA Publishing/DTIP 2007 ISBN: 978-2-35500-000-3